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Introduction to Parallel Computing Tutorial

Table of Contents

Abstract Parallel Computing Overview What is Parallel Computing? Why Use Parallel Computing?  Who is Using Parallel Computing? Concepts and Terminology von Neumann Computer Architecture Flynn's Taxonomy Some General Parallel Terminology Limits and Costs of Parallel Programming Parallel Computer Memory Architectures Shared Memory Distributed Memory Hybrid Distributed-Shared Memory Parallel Programming Models Parallel Programming Models Overview Shared Memory Model Threads Model Distributed Memory / Message Passing Model Data Parallel Model Hybrid Model SPMD and MPMP Designing Parallel Programs Automatic vs. Manual Parallelization Understand the Problem and the Program Partitioning Communications Synchronization Data Dependencies Load Balancing Granularity I/O Debugging Performance Analysis and Tuning Parallel Examples Array Processing  PI Calculation Simple Heat Equation 1-D Wave Equation References and More Information


This is the first instructional in the "Livermore Computing Getting Started" workshop. It is intended to supply just a brief evaluation of the in depth and vast subject of Parallel Computing, as a lead-in for the tutorials that observe it. As such, it covers simply the very basics of parallel computing, and is intended for anyone who is simply becoming acquainted with the topic and who's making plans to wait a number of of the other tutorials in this workshop. It isn't intended to cover Parallel Programming extensive, as this will require considerably extra time. The tutorial starts with a dialogue on parallel computing - what it is and the way it is used, followed by a discussion on ideas and terminology related to parallel computing. The topics of parallel memory architectures and programming fashions are then explored. These topics are adopted by way of a chain of sensible discussions on a host of the complex problems associated with designing and running parallel programs. The instructional concludes with several examples of learn how to parallelize simple serial programs. References are included for additional self-study.


What is Parallel Computing? Serial Computing

 Traditionally, device has been written for serial computation:

A problem is broken right into a discrete collection of directions Instructions are finished sequentially one after any other Executed on a single processor Only one instruction would possibly execute at any moment in time

 For example:

Parallel Computing

In the most simple sense, parallel computing is the simultaneous use of multiple compute sources to solve a computational downside:

An issue is broken into discrete parts that can be solved concurrently Each section is additional broken down to a series of directions Instructions from each section execute concurrently on different processors An overall control/coordination mechanism is hired

For example:

The computational drawback should be capable to: Be damaged aside into discrete pieces of paintings that may be solved concurrently; Execute more than one program directions at any second in time; Be solved in less time with more than one compute resources than with a unmarried compute resource. The compute resources are usually: A single pc with more than one processors/cores An arbitrary quantity of such computer systems hooked up via a network Parallel Computers Virtually all stand-alone computer systems lately are parallel from a hardware viewpoint: Multiple practical devices (L1 cache, L2 cache, branch, prefetch, decode, floating-point, graphics processing (GPU), integer, and many others.) Multiple execution devices/cores Multiple hardware threads IBM BG/Q Compute Chip with 18 cores (PU) and Sixteen L2 Cache units (L2) Networks connect a couple of stand-alone computers (nodes) to make larger parallel laptop clusters.


For example, the schematic underneath presentations a normal LLNL parallel computer cluster: Each compute node is a multi-processor parallel computer in itself Multiple compute nodes are networked along with an Infiniband community Special goal nodes, additionally multi-processor, are used for different purposes The majority of the arena's large parallel computers (supercomputers) are clusters of hardware produced by way of a handful of (mostly) well known vendors.

Source: Top500.org

Why Use Parallel Computing? The Real World is Massively Complex In the natural world, many complicated, interrelated events are happening on the identical time, but within a temporal collection. Compared to serial computing, parallel computing is far better fitted to modeling, simulating and understanding complicated, real global phenomena. For example, imagine modeling these serially:


Main Reasons SAVE TIME AND/OR MONEY In idea, throwing extra resources at a task will shorten its time to of entirety, with attainable value savings. Parallel computers can also be built from reasonable, commodity substances. SOLVE LARGER / MORE COMPLEX PROBLEMS Many problems are so huge and/or advanced that it is impractical or not possible to unravel them using a serial program, especially given restricted laptop memory. Example: "Grand Challenge Problems" (en.wikipedia.org/wiki/Grand_Challenge) requiring petaflops and petabytes of computing assets. Example: Web serps/databases processing hundreds of thousands of transactions every second PROVIDE CONCURRENCY A single compute useful resource can best do something at a time. Multiple compute assets can do many things simultaneously. Example: Collaborative Networks supply an international venue the place other folks from all over the world can meet and behavior work "virtually". TAKE ADVANTAGE OF NON-LOCAL RESOURCES Using compute assets on a wide area community, or even the Internet when local compute assets are scarce or inadequate. Example: [email protected] (setiathome.berkeley.edu) has over 1.7 million customers in nearly each and every nation on this planet. (May, 2018). MAKE BETTER USE OF UNDERLYING PARALLEL HARDWARE Modern computers, even laptops, are parallel in architecture with multiple processors/cores. Parallel tool is particularly intended for parallel hardware with multiple cores, threads, and so on. In maximum cases, serial techniques run on fashionable computers "waste" attainable computing energy. The Future During the previous 20+ years, the tendencies indicated by way of ever quicker networks, distributed techniques, and multi-processor laptop architectures (even on the desktop stage) obviously display that parallelism is the future of computing. In this identical period of time, there was a greater than 500,000x build up in supercomputer efficiency, with no end these days in sight. The race is already on for Exascale Computing - we're getting into Exascale era

Source: Top500.org

Who is Using Parallel Computing? Science and Engineering Historically, parallel computing has been considered to be "the high end of computing", and has been used to fashion difficult issues in many spaces of science and engineering: Atmosphere, Earth, Environment Physics - implemented, nuclear, particle, condensed topic, top drive, fusion, photonics Bioscience, Biotechnology, Genetics Chemistry, Molecular Sciences Geology, Seismology Mechanical Engineering - from prosthetics to spacecraft Electrical Engineering, Circuit Design, Microelectronics Computer Science, Mathematics Defense, Weapons Industrial and Commercial Today, industrial packages supply an equivalent or higher motive force in the development of faster computer systems. These applications require the processing of large quantities of data in sophisticated techniques. For instance: "Big Data", databases, data mining Artificial Intelligence (AI) Oil exploration Web engines like google, web based industry products and services Medical imaging and prognosis Pharmaceutical design Financial and financial modeling Management of nationwide and multi-national corporations Advanced graphics and digital fact, particularly within the entertainment industry Networked video and multi-media technologies Collaborative paintings environments Global Applications Parallel computing is now being used broadly around the world, in all kinds of programs.

Source: Top500.org

Source: Top500.org

Concepts and Terminology

von Neumann Architecture John von Neumann circa Forties(Source: LANL archives) Named after the Hungarian mathematician John von Neumann who first authored the overall necessities for an electronic laptop in his 1945 papers. Also known as "stored-program computer" - both program instructions and knowledge are saved in electronic memory. Differs from earlier computers that have been programmed via "hard wiring". Since then, virtually all computer systems have followed this elementary design: Comprised of 4 primary substances: Memory Control Unit Arithmetic Logic Unit Input/Output Read/write, random get right of entry to memory is used to store each program instructions and data

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<li>Program instructions are coded data which inform the computer to do one thing</li><li>Data is just data to be used by way of this system</li></ol>

Control unit fetches instructions/knowledge from memory, decodes the directions after which sequentially coordinates operations to perform the programmed assignment. Arithmetic Unit performs elementary mathematics operations Input/Output is the interface to the human operator More information on his other outstanding accomplishments: http://en.wikipedia.org/wiki/John_von_Neumann So what? Who cares? Well, parallel computer systems nonetheless apply this fundamental design, just multiplied in gadgets. The fundamental, fundamental architecture stays the similar. Flynn's Classical Taxonomy There are different ways to categorise parallel computer systems. Examples are available in the references. One of the more extensively used classifications, in use since 1966, is known as Flynn's Taxonomy. Flynn's taxonomy distinguishes multi-processor computer architectures according to how they are able to be categorised alongside the two impartial dimensions of Instruction Stream and Data Stream. Each of these dimensions can have just one of two imaginable states: Single or Multiple. The matrix below defines the Four conceivable classifications consistent with Flynn: Single Instruction, Single Data (SISD) A serial (non-parallel) pc Single Instruction: Only one instruction flow is being acted on through the CPU all through anyone clock cycle Single Data: Only one information circulation is being used as enter all over any one clock cycle Deterministic execution This is the oldest kind of pc Examples: older era mainframes, minicomputers, workstations and unmarried processor/core PCs. Single Instruction, Multiple Data (SIMD) A type of parallel laptop Single Instruction: All processing units execute the same instruction at any given clock cycle Multiple Data: Each processing unit can operate on a special knowledge part Best suited for specialised problems characterized via a high stage of regularity, comparable to graphics/image processing. Synchronous (lockstep) and deterministic execution Two varieties: Processor Arrays and Vector Pipelines Examples: Processor Arrays: Thinking Machines CM-2, MasPar MP-1 & MP-2, ILLIAC IV Vector Pipelines: IBM 9000, Cray X-MP, Y-MP & C90, Fujitsu VP, NEC SX-2, Hitachi S820, ETA10 Most trendy computers, specifically the ones with graphics processor devices (GPUs) make use of SIMD directions and execution units. Multiple Instruction, Single Data (MISD) A type of parallel pc Multiple Instruction: Each processing unit operates on the knowledge independently by means of separate instruction streams. Single Data: A unmarried data movement is fed into more than one processing gadgets. Few (if any) actual examples of this magnificence of parallel laptop have ever existed. Some conceivable uses could be: a couple of frequency filters operating on a single signal circulation multiple cryptography algorithms attempting to crack a single coded message.

Multiple Instruction, Multiple Data (MIMD)

A type of parallel laptop Multiple Instruction: Every processor may be executing a unique instruction movement Multiple Data: Every processor may be operating with a unique data move Execution may also be synchronous or asynchronous, deterministic or non-deterministic Currently, the most typical type of parallel laptop - most current supercomputers fall into this class. Examples: most present supercomputers, networked parallel computer clusters and "grids", multi-processor SMP computers, multi-core PCs. Note many MIMD architectures additionally include SIMD execution sub-components Some General Parallel Terminology Like the whole thing else, parallel computing has its own "jargon". Some of the more regularly used terms related to parallel computing are listed underneath. Most of those can be mentioned in additional detail later. Supercomputing / High Performance Computing (HPC)

Using the world's quickest and biggest computers to resolve large problems.


A standalone "computer in a box". Usually comprised of more than one CPUs/processors/cores, memory, network interfaces, and many others. Nodes are networked in combination to include a supercomputer.

CPU / Socket / Processor / Core

This varies, relying upon who you communicate to. In the previous, a CPU (Central Processing Unit) used to be a novel execution component for a pc. Then, more than one CPUs had been included right into a node. Then, person CPUs had been subdivided into multiple "cores", each and every being a singular execution unit. CPUs with more than one cores are also known as "sockets" - seller dependent. The result's a node with a couple of CPUs, every containing more than one cores. The nomenclature is perplexed every now and then. Wonder why?


A logically discrete segment of computational work. A job is typically a program or program-like set of directions this is achieved by way of a processor. A parallel program is composed of a couple of tasks operating on a couple of processors.


Breaking a job into steps carried out via different processor units, with inputs streaming via, just like an meeting line; a sort of parallel computing.

Shared Memory

From a strictly hardware point of view, describes a pc structure where all processors have direct (usually bus based) get admission to to not unusual physical memory. In a programming sense, it describes a fashion the place parallel tasks all have the same "picture" of memory and can at once address and get entry to the similar logical memory locations regardless of the place the bodily memory actually exists.

Symmetric Multi-Processor (SMP)

Shared memory hardware architecture the place multiple processors proportion a single cope with house and have equivalent get right of entry to to all assets.

Distributed Memory

In hardware, refers to community based memory access for bodily memory that is not commonplace. As a programming type, duties can best logically "see" local machine memory and must use communications to get entry to memory on different machines where different duties are executing.


Parallel duties typically want to exchange data. There are several ways this may also be accomplished, such as thru a shared memory bus or over a network, alternatively the true tournament of data change is frequently known as communications regardless of the method hired.


The coordination of parallel tasks in actual time, very continuously related to communications. Often implemented by setting up a synchronization level inside of an utility the place a job would possibly not continue additional till any other project(s) reaches the similar or logically an identical level.

Synchronization in most cases comes to ready through a minimum of one assignment, and will due to this fact motive a parallel application's wall clock execution time to extend.


In parallel computing, granularity is a qualitative measure of the ratio of computation to verbal exchange.

Coarse: slightly massive amounts of computational work are achieved between verbal exchange events Fine: fairly small amounts of computational work are completed between communication occasions Observed Speedup

Observed speedup of a code which has been parallelized, defined as:

wall-clock time of serial execution ----------------------------------- wall-clock time of parallel execution

One of the most simple and most generally used signs for a parallel program's performance.

Parallel Overhead

The amount of time required to coordinate parallel duties, as opposed to doing helpful work. Parallel overhead can include components corresponding to:

Task start-up time Synchronizations Data communications Software overhead imposed by means of parallel languages, libraries, working machine, and so forth. Task termination time Massively Parallel

Refers to the hardware that comprises a given parallel system - having many processing parts. The which means of "many" keeps expanding, however these days, the most important parallel computers are comprised of processing parts numbering in the loads of thousands to tens of millions.

Embarrassingly Parallel

Solving many identical, however impartial tasks concurrently; little to no want for coordination between the duties.


Refers to a parallel device's (hardware and/or device) ability to display a proportionate build up in parallel speedup with the addition of more assets. Factors that give a contribution to scalability include:

Hardware - in particular memory-cpu bandwidths and community communique houses Application set of rules Parallel overhead comparable Characteristics of your specific application Limits and Costs of Parallel Programming Amdahl's Law Amdahl's Law states that doable program speedup is defined by way of the fraction of code (P) that may be parallelized: 1 speedup = -------- 1 - PIf none of the code can also be parallelized, P = 0 and the speedup = 1 (no speedup). If all of the code is parallelized, P = 1 and the speedup is countless (in concept). If 50% of the code may also be parallelized, most speedup = 2, which means the code will run twice as rapid. Introducing the quantity of processors performing the parallel fraction of work, the connection can also be modeled by means of: 1 speedup = ------------ P + S --- Nwhere P = parallel fraction, N = number of processors and S = serial fraction.


It quickly turns into obvious that there are limits to the scalability of parallelism. For instance: speedup ------------------------------------- N P = .50 P = .90 P = .95 P = .99 ----- ------- ------- ------- ------- 10 1.82 5.26 6.89 9.17 100 1.98 9.17 16.80 50.25 1,000 1.99 9.91 19.62 90.99 10,000 1.99 9.91 19.96 99.02 100,000 1.99 9.99 19.99 99.90"Famous" quote: You can spend a life-time getting 95% of your code to be parallel, and not succeed in higher than 20x speedup no matter how many processors you throw at it! However, certain problems display greater efficiency by way of increasing the problem measurement. For example: 2D Grid Calculations Parallel fraction 85 seconds 85% Serial fraction 15 seconds 15% We can increase the issue measurement through doubling the grid dimensions and halving the time step. This leads to four instances the quantity of grid issues and twice the quantity of time steps. The timings then seem like: 2D Grid Calculations Parallel fraction 680 seconds 97.84% Serial fraction 15 seconds 2.16% Problems that building up the percentage of parallel time with their size are extra scalable than issues of a hard and fast percentage of parallel time. Complexity In general, parallel packages are much more advanced than corresponding serial programs, in all probability an order of magnitude. Not simplest do you have more than one instruction streams executing at the identical time, however you additionally have knowledge flowing between them. The prices of complexity are measured in programmer time in nearly every aspect of the instrument development cycle: Design Coding Debugging Tuning Maintenance Adhering to "good" software construction practices is essential when operating with parallel applications - especially if any person but even so you'll have to paintings with the device. Portability Thanks to standardization in several APIs, similar to MPI, POSIX threads, and OpenMP, portability issues with parallel programs aren't as critical as in years previous. However... All of the usual portability problems related to serial programs practice to parallel techniques. For instance, in case you use vendor "enhancements" to Fortran, C or C++, portability will likely be an issue. Even regardless that standards exist for several APIs, implementations will vary in a number of main points, occasionally to the purpose of requiring code modifications to be able to effect portability. Operating systems can play a key function in code portability problems. Hardware architectures are characteristically highly variable and will impact portability. Resource Requirements The primary intent of parallel programming is to lower execution wall clock time, however to be able to accomplish this, extra CPU time is needed. For instance, a parallel code that runs in 1 hour on 8 processors actually uses 8 hours of CPU time. The amount of memory required can also be better for parallel codes than serial codes, due to the want to reflect knowledge and for overheads related to parallel strengthen libraries and subsystems. For short working parallel systems, there can in truth be a decrease in efficiency compared to a an identical serial implementation. The overhead prices related to setting up the parallel atmosphere, assignment introduction, communications and task termination can comprise a good portion of the entire execution time for short runs. Scalability Two varieties of scaling based on time to answer: robust scaling and weak scaling. Strong scaling: The general downside size stays fixed as extra processors are added. Goal is to run the same drawback size sooner Perfect scaling way drawback is solved in 1/P time (compared to serial) Weak scaling: The drawback measurement according to processor stays mounted as more processors are added. The total downside measurement is proportional to the number of processors used. Goal is to run higher problem in identical quantity of time Perfect scaling method downside Px runs in same time as single processor run The ability of a parallel program's performance to scale is a consequence of a number of interrelated factors. Simply adding extra processors is never the solution. The algorithm might have inherent limits to scalability. At some level, including extra resources causes performance to lower. This is a commonplace state of affairs with many parallel programs. Hardware components play a vital function in scalability. Examples: Memory-cpu bus bandwidth on an SMP machine Communications community bandwidth Amount of memory to be had on any given device or set of machines Processor clock pace Parallel beef up libraries and subsystems instrument can limit scalability impartial of your software.

Parallel Computer Memory Architectures

Shared Memory General Characteristics Shared memory parallel computer systems vary broadly, however in most cases have in common the facility for all processors to get entry to all memory as global address house. Multiple processors can perform independently but share the similar memory resources. Changes in a memory location effected through one processor are visible to all different processors. Historically, shared memory machines have been categorized as UMA and NUMA, primarily based upon memory access instances. Uniform Memory Access (UMA) Most commonly represented nowadays through Symmetric Multiprocessor (SMP) machines Identical processors Equal get right of entry to and access instances to memory Sometimes referred to as CC-UMA - Cache Coherent UMA. Cache coherent manner if one processor updates a location in shared memory, all the different processors know about the replace. Cache coherency is achieved at the hardware stage. Non-Uniform Memory Access (NUMA) Often made by means of physically linking two or extra SMPs One SMP can immediately get entry to memory of any other SMP Not all processors have equal get admission to time to all memories Memory access across link is slower If cache coherency is maintained, then may also be known as CC-NUMA - Cache Coherent NUMA Advantages Global cope with area provides a user-friendly programming viewpoint to memory Data sharing between duties is both rapid and uniform because of the proximity of memory to CPUs Disadvantages Primary drawback is the shortage of scalability between memory and CPUs. Adding more CPUs can geometrically increases site visitors on the shared memory-CPU trail, and for cache coherent techniques, geometrically increase traffic related to cache/memory management. Programmer responsibility for synchronization constructs that be sure that "correct" get entry to of world memory. Distributed Memory General Characteristics Like shared memory systems, dispensed memory techniques range extensively but share a not unusual function. Distributed memory techniques require a communication network to connect inter-processor memory. Processors have their very own native memory. Memory addresses in one processor do not map to every other processor, so there may be no idea of global deal with house throughout all processors. Because each processor has its personal local memory, it operates independently. Changes it makes to its local memory have no effect at the memory of other processors. Hence, the concept that of cache coherency does no longer practice. When a processor wishes get admission to to information in any other processor, it is typically the duty of the programmer to explicitly outline how and when knowledge is communicated. Synchronization between duties is likewise the programmer's responsibility. The community "fabric" used for knowledge switch varies broadly, despite the fact that it may be so simple as Ethernet. Advantages Memory is scalable with the quantity of processors. Increase the number of processors and the scale of memory will increase proportionately. Each processor can unexpectedly get right of entry to its personal memory with out interference and without the overhead incurred with seeking to care for international cache coherency. Cost effectiveness: can use commodity, off-the-shelf processors and networking. Disadvantages The programmer is responsible for lots of of the details related to information verbal exchange between processors. It is also tough to map current information constructions, in line with world memory, to this memory group. Non-uniform memory get admission to instances - data living on a far flung node takes longer to get right of entry to than node native information. Hybrid Distributed-Shared Memory General Characteristics The greatest and fastest computers on the earth lately make use of both shared and dispensed memory architectures. The shared memory part generally is a shared memory machine and/or graphics processing devices (GPU). The distributed memory element is the networking of more than one shared memory/GPU machines, which know handiest about their very own memory - no longer the memory on another gadget. Therefore, network communications are required to transport knowledge from one device to any other. Current tendencies seem to suggest that this type of memory architecture will proceed to succeed and build up at the high end of computing for the foreseeable future. Advantages and Disadvantages Whatever is common to both shared and distributed memory architectures. Increased scalability is the most important benefit Increased programmer complexity is the most important downside

Parallel Programming Models

Overview There are a number of parallel programming fashions in common use: Shared Memory (with out threads) Threads Distributed Memory / Message Passing Data Parallel Hybrid Single Program Multiple Data (SPMD) Multiple Program Multiple Data (MPMD) Parallel programming fashions exist as an abstraction above hardware and memory architectures. Although it will no longer appear apparent, those models are NOT explicit to a particular kind of machine or memory structure. In reality, any of those fashions can (theoretically) be carried out on any underlying hardware. Two examples from the past are discussed under. SHARED memory model on a DISTRIBUTED memory device

Kendall Square Research (KSR) ALLCACHE approach. Machine memory used to be physically distributed across networked machines, but gave the impression to the person as a unmarried shared memory global cope with area. Generically, this manner is referred to as "virtual shared memory".

DISTRIBUTED memory fashion on a SHARED memory system

Message Passing Interface (MPI) on SGI Origin 2000. The SGI Origin 2000 employed the CC-NUMA type of shared memory architecture, the place each and every task has direct access to global cope with area unfold throughout all machines. However, the power to send and obtain messages using MPI, as is repeatedly executed over a network of disbursed memory machines, used to be applied and frequently used.

Which fashion to use? This is frequently a combination of what is available and personal choice. There is no "best" type, although there for sure are higher implementations of some models over others. The following sections describe each of the fashions discussed above, and likewise discuss some of their actual implementations. Shared Memory Model (without threads) In this programming model, processes/tasks proportion a common address area, which they learn and write to asynchronously. Various mechanisms comparable to locks / semaphores are used to keep an eye on get entry to to the shared memory, get to the bottom of contentions and to prevent race conditions and deadlocks. This is in all probability the most straightforward parallel programming model. An advantage of this type from the programmer's level of view is that the perception of data "ownership" is missing, so there may be no need to specify explicitly the communication of information between tasks. All processes see and have equal get right of entry to to shared memory. Program development can frequently be simplified. An essential disadvantage in terms of efficiency is that it becomes extra difficult to understand and organize information locality: Keeping information native to the process that works on it conserves memory accesses, cache refreshes and bus visitors that happens when more than one processes use the same knowledge. Unfortunately, controlling information locality is tricky to know and may be past the keep watch over of the common user.


On stand-alone shared memory machines, local running techniques, compilers and/or hardware provide beef up for shared memory programming. For example, the POSIX usual provides an API for using shared memory, and UNIX provides shared memory segments (shmget, shmat, shmctl, and so on). On disbursed memory machines, memory is bodily dispensed across a network of machines, however made international thru specialized hardware and device. A variety of SHMEM implementations are available: http://en.wikipedia.org/wiki/SHMEM. Threads Model This programming style is a type of shared memory programming. In the threads style of parallel programming, a single "heavy weight" process can have multiple "light weight", concurrent execution paths. For example: The primary program a.out is scheduled to run by the native running system. a.out lots and acquires all of the vital system and consumer resources to run. This is the "heavy weight" procedure. a.out performs some serial work, and then creates a bunch of duties (threads) that may be scheduled and run through the running system similtaneously. Each thread has native data, but additionally, stocks the entire resources of a.out. This saves the overhead related to replicating a program's assets for each thread ("light weight"). Each thread also advantages from a global memory view because it shares the memory house of a.out. A thread's work would possibly highest be described as a subroutine within the principle program. Any thread can execute any subroutine similtaneously other threads. Threads be in contact with each different through international memory (updating deal with places). This requires synchronization constructs to make certain that multiple thread is not updating the similar international address at any time. Threads can come and move, however a.out remains present to provide the necessary shared sources until the appliance has finished.


From a programming perspective, threads implementations frequently include: A library of subroutines which are referred to as from inside parallel supply code A set of compiler directives imbedded in both serial or parallel source code

In both circumstances, the programmer is accountable for figuring out the parallelism (even supposing compilers can every now and then lend a hand).

Threaded implementations aren't new in computing. Historically, hardware distributors have applied their own proprietary versions of threads. These implementations differed considerably from each other making it difficult for programmers to broaden portable threaded applications. Unrelated standardization efforts have led to two very different implementations of threads: POSIX Threads and OpenMP. POSIX Threads Specified by the IEEE POSIX 1003.1c standard (1995). C Language handiest. Part of Unix/Linux working methods Library based totally Commonly referred to as Pthreads. Very particular parallelism; calls for significant programmer consideration to element. OpenMP  Industry usual, jointly outlined and recommended through a bunch of most important computer hardware and tool distributors, organizations and people. Compiler directive primarily based Portable / multi-platform, together with Unix and Windows platforms Available in C/C++ and Fortran implementations Can be really easy and simple to make use of - provides for "incremental parallelism". Can begin with serial code. Other threaded implementations are common, but now not mentioned here: Microsoft threads Java, Python threads CUDA threads for GPUs More Information Distributed Memory / Message Passing Model This type demonstrates the following characteristics: A suite of duties that use their own local memory during computation. Multiple tasks can live at the identical bodily machine and/or across an arbitrary number of machines. Tasks change information via communications by sending and receiving messages. Data switch normally requires cooperative operations to be carried out by way of each procedure. For example, a send operation should have a matching receive operation.


From a programming point of view, message passing implementations typically include a library of subroutines. Calls to those subroutines are imbedded in source code. The programmer is chargeable for determining all parallelism. Historically, a wide range of message passing libraries have been to be had for the reason that 1980s. These implementations differed substantially from every other making it tough for programmers to expand transportable packages. In 1992, the MPI Forum was formed with the principle purpose of organising a typical interface for message passing implementations. Part 1 of the Message Passing Interface (MPI) was released in 1994. Part 2 (MPI-2) was once released in 1996 and MPI-Three in 2012. All MPI specifications are available on the internet at http://www.mpi-forum.org/docs/. MPI is the "de facto" trade usual for message passing, changing nearly all different message passing implementations used for manufacturing paintings. MPI implementations exist for nearly all widespread parallel computing platforms. Not all implementations include the whole thing in MPI-1, MPI-2 or MPI-3. More Information Data Parallel Model May also be known as the Partitioned Global Address Space (PGAS) model. The data parallel type demonstrates the next characteristics: Address house is treated globally Most of the parallel work specializes in acting operations on an information set. The information set is usually organized into a not unusual structure, such as an array or cube. A suite of duties work jointly at the same knowledge construction, then again, every project works on a distinct partition of the similar knowledge construction. Tasks perform the similar operation on their partition of work, as an example, "add 4 to every array element". On shared memory architectures, all tasks would possibly have access to the knowledge construction through international memory. On dispensed memory architectures, the worldwide information construction can also be cut up up logically and/or physically throughout duties.


Currently, there are several fairly well-liked, and on occasion developmental, parallel programming implementations in keeping with the Data Parallel / PGAS model. Coarray Fortran: a small set of extensions to Fortran 95 for SPMD parallel programming. Compiler dependent. More information: https://en.wikipedia.org/wiki/Coarray_Fortran Unified Parallel C (UPC): an extension to the C programming language for SPMD parallel programming. Compiler dependent. More knowledge: https://upc.lbl.gov/ Global Arrays: provides a shared memory taste programming environment within the context of allotted array information structures. Public area library with C and Fortran77 bindings. More information: https://en.wikipedia.org/wiki/Global_Arrays X10: a PGAS primarily based parallel programming language being developed by way of IBM at the Thomas J. Watson Research Center. More data: http://x10-lang.org/ Chapel: an open supply parallel programming language undertaking being led through Cray. More information: http://chapel.cray.com/ Hybrid Model A hybrid type combines multiple of the in the past described programming fashions. Currently, a commonplace instance of a hybrid style is the combo of the message passing fashion (MPI) with the threads fashion (OpenMP). Threads carry out computationally in depth kernels using native, on-node information Communications between processes on other nodes occurs over the community the use of MPI This hybrid style lends itself smartly to the preferred (recently) hardware setting of clustered multi/many-core machines. Another equivalent and an increasing number of well-liked example of a hybrid model is using MPI with CPU-GPU (Graphics Processing Unit) programming. MPI duties run on CPUs the usage of native memory and speaking with every different over a community. Computationally extensive kernels are off-loaded to GPUs on-node. Data change between node-local memory and GPUs makes use of CUDA (or one thing equivalent). Other hybrid fashions are commonplace: MPI with Pthreads MPI with non-GPU accelerators ... SPMD and MPMD Single Program Multiple Data (SPMD) SPMD is in fact a "high level" programming type that may be built upon any combination of the previously discussed parallel programming models. SINGLE PROGRAM: All duties execute their copy of the similar program concurrently. This program can be threads, message passing, information parallel or hybrid. MULTIPLE DATA: All tasks would possibly use different knowledge SPMD methods generally have the important good judgment programmed into them to permit other duties to branch or conditionally execute best those parts of the program they're designed to execute. That is, tasks do not necessarily have to execute the entire program - in all probability only a portion of it. The SPMD fashion, the usage of message passing or hybrid programming, is some of the frequently used parallel programming style for multi-node clusters. Multiple Program Multiple Data (MPMD) Like SPMD, MPMD is in reality a "high level" programming model that may be constructed upon any combination of the previously mentioned parallel programming fashions. MULTIPLE PROGRAM: Tasks may execute other programs simultaneously. The systems may also be threads, message passing, data parallel or hybrid. MULTIPLE DATA: All tasks would possibly use different knowledge MPMD applications are not as common as SPMD programs, however could also be better suited to certain types of issues, particularly those who lend themselves higher to practical decomposition than domain decomposition (mentioned later below Partitioning).

Designing Parallel Programs

Automatic vs. Manual Parallelization Designing and creating parallel systems has characteristically been a very manual procedure. The programmer is most often responsible for each figuring out and in truth implementing parallelism. Very frequently, manually growing parallel codes is a time consuming, complicated, error-prone and iterative procedure. For a bunch of years now, various equipment have been to be had to assist the programmer with changing serial programs into parallel programs. The maximum commonplace sort of tool used to robotically parallelize a serial program is a parallelizing compiler or pre-processor. A parallelizing compiler in most cases works in two alternative ways: Fully Automatic The compiler analyzes the supply code and identifies opportunities for parallelism. The analysis includes figuring out inhibitors to parallelism and perhaps a value weighting on whether or now not the parallelism would if truth be told give a boost to efficiency. Loops (do, for) are essentially the most widespread target for computerized parallelization. Programmer Directed Using "compiler directives" or most likely compiler flags, the programmer explicitly tells the compiler how you can parallelize the code. May be capable of be used at the side of some extent of automated parallelization additionally. The maximum not unusual compiler generated parallelization is completed using on-node shared memory and threads (akin to OpenMP). If you're beginning with an current serial code and have time or budget constraints, then automated parallelization is also the solution. However, there are a number of important caveats that practice to computerized parallelization: Wrong results is also produced Performance would possibly actually degrade Much much less versatile than guide parallelization Limited to a subset (mostly loops) of code May if truth be told now not parallelize code if the compiler analysis suggests there are inhibitors or the code is simply too advanced The the rest of this section applies to the manual means of developing parallel codes. Understand the Problem and the Program Undoubtedly, the first step in growing parallel device is to first understand the problem that you want to remedy in parallel. If you might be beginning with a serial program, this necessitates figuring out the present code also. Before spending time in an attempt to broaden a parallel solution for a problem, decide whether or not or now not the problem is one that can in truth be parallelized. Example of an easy-to-parallelize problem:

Calculate the prospective power for each of a number of thousand impartial conformations of a molecule. When completed, to find the minimum power conformation.

This problem is able to be solved in parallel. Each of the molecular conformations is independently determinable. The calculation of the minimum energy conformation is also a parallelizable drawback.

Example of an issue with little-to-no parallelism:

Calculation of the Fibonacci series (0,1,1,2,3,5,8,13,21,...) by use of the formulation:F(n) = F(n-1) + F(n-2)

The calculation of the F(n) price uses the ones of each F(n-1) and F(n-2), which will have to be computed first.

Identify this system's hotspots: Know the place maximum of the true work is being done. The majority of medical and technical programs usually accomplish most of their work in a couple of places. Profilers and performance research gear can lend a hand right here Focus on parallelizing the hotspots and ignore the ones sections of this system that account for little CPU utilization. Identify bottlenecks in this system: Are there areas that are disproportionately gradual, or purpose parallelizable work to halt or be deferred? For instance, I/O is generally something that slows a program down. May be imaginable to restructure the program or use a unique algorithm to cut back or get rid of unnecessary gradual areas Identify inhibitors to parallelism. One common elegance of inhibitor is knowledge dependence, as demonstrated by way of the Fibonacci collection above. Investigate different algorithms if imaginable. This could also be the only maximum important consideration when designing a parallel software. Take benefit of optimized third celebration parallel instrument and highly optimized math libraries to be had from leading vendors (IBM's ESSL, Intel's MKL, AMD's AMCL, and so forth.). Partitioning One of the first steps in designing a parallel program is to damage the issue into discrete "chunks" of work that may be disbursed to a couple of tasks. This is referred to as decomposition or partitioning. There are two basic tactics to partition computational paintings among parallel duties: domain decomposition and useful decomposition. Domain Decomposition In this sort of partitioning, the data related to a problem is decomposed. Each parallel project then works on a portion of the knowledge. There are different ways to partition knowledge: Functional Decomposition In this approach, the focus is on the computation this is to be carried out moderately than on the information manipulated by the computation. The problem is decomposed in line with the paintings that will have to be completed. Each assignment then plays a portion of the entire paintings. Functional decomposition lends itself neatly to problems that may be break up into different tasks. For example: Ecosystem Modeling

Each program calculates the population of a given group, the place every group's enlargement depends upon that of its neighbors. As time progresses, each and every procedure calculates its present state, then exchanges information with the neighbor populations. All duties then growth to calculate the state on the subsequent time step.

Signal Processing

An audio signal information set is passed via four distinct computational filters. Each filter is a separate process. The first phase of information should move throughout the first filter prior to progressing to the second one. When it does, the second section of information passes through the first clear out. By the time the fourth phase of information is within the first filter out, all four tasks are busy.

Climate Modeling

Each fashion part can also be concept of as a separate project. Arrows represent exchanges of knowledge between ingredients all the way through computation: the ambience model generates wind pace data which are utilized by the ocean fashion, the ocean type generates sea floor temperature knowledge which are utilized by the atmosphere model, and so forth.

Combining those two sorts of downside decomposition is not unusual and herbal. Communications Who Needs Communications? The need for communications between tasks will depend on your drawback: You DON'T want communications Some varieties of problems can be decomposed and done in parallel with just about no need for tasks to percentage information. These sorts of problems are regularly referred to as embarrassingly parallel - little or no communications are required. For example, imagine an image processing operation the place each pixel in a black and white symbol must have its colour reversed. The image information can easily be allotted to a couple of tasks that then act independently of each and every different to do their portion of the work. You DO want communications Most parallel applications aren't rather so simple, and do require tasks to proportion knowledge with each different. For instance, a 2-D warmth diffusion problem calls for a role to know the temperatures calculated through the tasks that have neighboring data. Changes to neighboring knowledge has an instantaneous effect on that task's information. Factors to Consider

There are a number of necessary elements to imagine when designing your program's inter-task communications:

Communication overhead Inter-task verbal exchange virtually at all times implies overhead. Machine cycles and assets that may be used for computation are as a substitute used to package deal and transmit knowledge. Communications frequently require some kind of synchronization between tasks, which may end up in duties spending time "waiting" instead of doing work. Competing verbal exchange visitors can saturate the to be had community bandwidth, additional stressful performance issues. Latency vs. Bandwidth Latency is the time it takes to ship a minimum (0 byte) message from point A to point B. Commonly expressed as microseconds. Bandwidth is the amount of knowledge that can be communicated in line with unit of time. Commonly expressed as megabytes/sec or gigabytes/sec. Sending many small messages may cause latency to dominate conversation overheads. Often it is more environment friendly to bundle small messages into a bigger message, thus increasing the effective communications bandwidth. Visibility of communications With the Message Passing Model, communications are explicit and most often moderately visual and beneath the regulate of the programmer. With the Data Parallel Model, communications regularly occur transparently to the programmer, specifically on dispensed memory architectures. The programmer won't even be capable to know precisely how inter-task communications are being completed. Synchronous vs. asynchronous communications Synchronous communications require some sort of "handshaking" between tasks which might be sharing knowledge. This can also be explicitly structured in code by way of the programmer, or it is going to occur at a lower degree unknown to the programmer. Synchronous communications are steadily referred to as blocking off communications since different work should wait till the communications have completed. Asynchronous communications permit tasks to transfer information independently from one any other. For example, project 1 can prepare and send a message to project 2, and then straight away start doing other work. When task 2 if truth be told receives the information does not topic. Asynchronous communications are regularly referred to as non-blocking communications since different work can be carried out while the communications are taking place. Interleaving computation with verbal exchange is the one largest receive advantages for the use of asynchronous communications. Scope of communications Knowing which tasks must keep up a correspondence with each and every different is important during the design level of a parallel code. Both of the 2 scopings described underneath may also be carried out synchronously or asynchronously. Point-to-point - comes to two duties with one task performing as the sender/producer of knowledge, and the opposite performing because the receiver/shopper. Collective - comes to data sharing between greater than two tasks, that are often specified as being contributors in a commonplace workforce, or collective. Some not unusual diversifications (there are more): Efficiency of communications Oftentimes, the programmer has alternatives that may affect communications efficiency. Only a few are mentioned right here. Which implementation for a given style must be used? Using the Message Passing Model as an example, one MPI implementation could also be sooner on a given hardware platform than any other. What sort of conversation operations will have to be used? As mentioned previously, asynchronous conversation operations can strengthen general program efficiency. Network fabric—other platforms use other networks. Some networks perform higher than others. Choosing a platform with a sooner network may be an option. Overhead and Complexity Finally, notice that this is just a partial listing of things to consider! Synchronization Managing the collection of paintings and the tasks appearing this is a important design consideration for most parallel methods. Can be a significant component in program performance (or lack of it) Often calls for "serialization" of segments of this system. Types of Synchronization Barrier Usually implies that all tasks are concerned Each project plays its work till it reaches the barrier. It then stops, or "blocks". When the closing project reaches the barrier, all tasks are synchronized. What happens from here varies. Often, a serial phase of paintings will have to be completed. In different instances, the tasks are automatically launched to continue their work. Lock / semaphore Can involve any quantity of tasks Typically used to serialize (protect) get entry to to international information or a piece of code. Only one task at a time might use (personal) the lock / semaphore / flag. The first project to obtain the lock "sets" it. This project can then safely (serially) get right of entry to the protected information or code. Other tasks can try to achieve the lock but will have to wait until the duty that owns the lock releases it. Can be blockading or non-blocking. Synchronous verbal exchange operations Involves most effective the ones tasks executing a communique operation. When a task plays a verbal exchange operation, some shape of coordination is needed with the other project(s) participating in the conversation. For instance, ahead of a task can perform a send operation, it will have to first obtain an acknowledgment from the receiving task that it's OK to send. Discussed in the past within the Communications phase. Data Dependencies Definition A dependence exists between program statements when the order of statement execution impacts the results of this system. A knowledge dependence results from a couple of use of the same location(s) in garage by way of different tasks. Dependencies are necessary to parallel programming because they're one of the main inhibitors to parallelism. Examples Loop carried information dependence DO J = MYSTART,MYEND A(J) = A(J-1) * 2.0 END DOThe value of A(J-1) should be computed prior to the worth of A(J), therefore A(J) exhibits a data dependency on A(J-1). Parallelism is inhibited. If Task 2 has A(J) and project 1 has A(J-1), computing the correct value of A(J) necessitates: Distributed memory architecture - project 2 will have to obtain the value of A(J-1) from assignment 1 after project 1 finishes its computation Shared memory architecture - project 2 should learn A(J-1) after project 1 updates it Loop independent information dependence assignment 1 task 2 ------ ------ X = 2 X = 4 . . . . Y = X**2 Y = X**3As with the previous example, parallelism is inhibited. The price of Y relies on: Distributed memory structure - if or when the price of X is communicated between the duties. Shared memory structure - which assignment final retail outlets the value of X. Although all information dependencies are vital to spot when designing parallel methods, loop carried dependencies are specifically important since loops are most likely the most typical goal of parallelization efforts. How to Handle Data Dependencies Distributed memory architectures - keep up a correspondence required knowledge at synchronization issues. Shared memory architectures -synchronize read/write operations between duties. Load Balancing Load balancing refers to the apply of distributing approximately equivalent amounts of paintings amongst duties so that all duties are saved busy all of the time. It will also be regarded as a minimization of project idle time. Load balancing is necessary to parallel programs for performance causes. For instance, if all duties are subject to a barrier synchronization level, the slowest task will resolve the entire performance. How to Achieve Load Balance Equally partition the work each project receives For array/matrix operations the place every task performs an identical work, evenly distribute the knowledge set a few of the tasks. For loop iterations where the paintings finished in each iteration is similar, flippantly distribute the iterations across the duties. If a heterogeneous mix of machines with varying efficiency characteristics are getting used, make sure you use some type of performance research instrument to detect any load imbalances. Adjust paintings accordingly. Use dynamic work assignment Certain classes of problems result in load imbalances even supposing knowledge is calmly disbursed among duties: Sparse arrays - some duties will have exact data to paintings on whilst others have most commonly "zeros". Adaptive grid strategies - some tasks may need to refine their mesh whilst others do not. N-body simulations - particles may migrate throughout task domains requiring extra work for some tasks. When the quantity of work each assignment will perform is deliberately variable, or is not able to be predicted, it may be useful to use a scheduler-task pool approach. As each assignment finishes its paintings, it receives a brand new piece from the work queue. Ultimately, it'll become essential to design an algorithm which detects and handles load imbalances as they occur dynamically inside the code. Granularity Computation / Communication Ratio In parallel computing, granularity is a qualitative measure of the ratio of computation to conversation. Periods of computation are generally separated from sessions of communication by way of synchronization occasions. Fine-grain Parallelism Relatively small quantities of computational work are accomplished between communication occasions. Low computation to communique ratio. Facilitates load balancing. Implies top conversation overhead and no more opportunity for performance enhancement. If granularity is just too wonderful it's imaginable that the overhead required for communications and synchronization between duties takes longer than the computation. Coarse-grain Parallelism Relatively massive amounts of computational paintings are accomplished between communique/synchronization events High computation to verbal exchange ratio Implies more alternative for performance building up Harder to load stability efficiently Which is Best? The most efficient granularity is dependent on the algorithm and the hardware atmosphere by which it runs. In most circumstances the overhead associated with communications and synchronization is prime relative to execution pace so it's effective to have coarse granularity. Fine-grain parallelism can assist reduce overheads due to load imbalance. I/O The Bad News I/O operations are in most cases regarded as inhibitors to parallelism. I/O operations require orders of magnitude more time than memory operations. Parallel I/O methods could also be immature or now not to be had for all platforms. In an atmosphere the place all duties see the similar file area, write operations can lead to file overwriting. Read operations may also be affected by the record server's talent to maintain more than one learn requests on the similar time. I/O that must be performed over the community (NFS, non-local) could cause critical bottlenecks and even crash report servers. The Good News Parallel record programs are to be had. For instance: The parallel I/O programming interface specification for MPI has been available since 1996 as part of MPI-2. Vendor and "free" implementations are now often available. A couple of pointers: Rule #1: Reduce overall I/O as much as conceivable. If you have get admission to to a parallel file device, use it. Writing large chunks of data quite than small chunks is typically significantly extra environment friendly. Fewer, larger information performs higher than many small information. Confine I/O to specific serial portions of the process, and then use parallel communications to distribute data to parallel duties. For instance, Task 1 may just learn an input document after which be in contact required data to different duties. Likewise, Task 1 could carry out write operation after receiving required knowledge from all different tasks. Aggregate I/O operations across duties - fairly than having many duties carry out I/O, have a subset of tasks perform it. Debugging Debugging parallel codes can be extremely difficult, specifically as codes scale upwards. The just right information is that there are some excellent debuggers to be had to lend a hand: Threaded - pthreads and OpenMP MPI GPU / accelerator Hybrid Livermore Computing customers have get right of entry to to a number of parallel debugging gear put in on LC's clusters: TotalView from RogueWave Software DDT from Allinea Inspector from Intel Stack Trace Analysis Tool (STAT) - in the community developed All of these tools have a finding out curve associated with them - some more than others. For main points and getting began data, see: Performance Analysis and Tuning As with debugging, inspecting and tuning parallel program efficiency will also be a lot more challenging than for serial methods. Fortunately, there are a number of very good gear for parallel program efficiency research and tuning. Livermore Computing customers have access to a number of such tools, most of which can be to be had on all manufacturing clusters. Some beginning points for equipment put in on LC systems:

Parallel Examples

Array Processing This instance demonstrates calculations on 2-dimensional array elements; a serve as is evaluated on each array element. The computation on every array part is independent from other array components. The drawback is computationally extensive. The serial program calculates one element at a time in sequential order. Serial code could be of the shape: do j = 1,n do i = 1,n a(i,j) = fcn(i,j) finish do finish doQuestions to ask: Is this drawback in a position to be parallelized? How would the problem be partitioned? Are communications needed? Are there any information dependencies? Are there synchronization wishes? Will load balancing be a priority? Parallel Solution 1 The calculation of elements is impartial of one another - results in an embarrassingly parallel resolution. Arrays components are calmly distributed so that every procedure owns a portion of the array (subarray). Distribution scheme is chosen for environment friendly memory access; e.g. unit stride (stride of 1) in the course of the subarrays. Unit stride maximizes cache/memory utilization. Since it is desirable to have unit stride through the subarrays, the selection of a distribution scheme is determined by the programming language. See the Block - Cyclic Distributions Diagram for the choices. Independent calculation of array elements guarantees there may be no want for conversation or synchronization between duties. Since the volume of work is lightly allotted throughout processes, there will have to no longer be load balance considerations. After the array is distributed, each and every assignment executes the portion of the loop similar to the knowledge it owns. For instance, both Fortran (column-major) and C (row-major) block distributions are shown:


do j = mystart, myend do i = 1, n a(i,j) = fcn(i,j) end do end do


for i (i = mystart; i < myend; i++)   for j (j = 0; j < n; j++)   a(i,j) = fcn(i,j);   Notice that only the outer loop variables are different from the serial answer. One Possible Solution: Implement as a Single Program Multiple Data (SPMD) type - every project executes the same program. Master procedure initializes array, sends data to employee processes and receives results. Worker process receives info, performs its percentage of computation and sends results to master. Using the Fortran storage scheme, carry out block distribution of the array. Pseudo code solution: purple highlights adjustments for parallelism. in finding out if I am MASTER or WORKER if I'm MASTER initialize the array send each and every WORKER information on section of array it owns ship each WORKER its portion of preliminary array receive from every WORKER results else if I'm WORKER obtain from MASTER info on section of array I own receive from MASTER my portion of initial array # calculate my portion of array do j = my first column,my closing column do i = 1,n a(i,j) = fcn(i,j) finish do finish do send MASTER results endifExample Programs Parallel Solution 2: Pool of Tasks The previous array answer demonstrated static load balancing: Each assignment has a set quantity of work to do May be vital idle time for faster or extra flippantly loaded processors - slowest tasks determines overall performance. Static load balancing is not generally a big worry if all tasks are performing the same amount of paintings on similar machines. If you have a load balance problem (some tasks paintings faster than others), you could benefit by means of using a "pool of tasks" scheme. Pool of Tasks Scheme Two processes are hired

Master Process:

Holds pool of duties for worker processes to do Sends worker a role when asked Collects results from workers

Worker Process: many times does the next

Gets task from master process Performs computation Sends effects to master Worker processes do not know prior to runtime which portion of array they're going to care for or how many tasks they're going to perform. Dynamic load balancing occurs at run time: the speedier duties will get extra paintings to do. Pseudo code solution: crimson highlights changes for parallelism. in finding out if I am MASTER or WORKER if I'm MASTER do till no more jobs if request send to WORKER subsequent activity else receive results from WORKER finish do else if I am WORKER do until no more jobs request task from MASTER obtain from MASTER next task calculate array part: a(i,j) = fcn(i,j) ship effects to MASTER finish do endifDiscussion In the above pool of tasks instance, each and every project calculated a person array part as a job. The computation to communique ratio is finely granular. Finely granular solutions incur extra conversation overhead with the intention to scale back task idle time. A more optimum resolution may well be to distribute extra paintings with each job. The "right" quantity of paintings is problem dependent. PI Calculation The worth of PI can be calculated in quite a lot of ways. Consider the Monte Carlo means of approximating PI: Inscribe a circle with radius r in a sq. with aspect duration of 2r The house of the circle is Πr2 and the area of the sq. is 4r2 The ratio of the realm of the circle to the area of the square is:Πr2 / 4r2 = Π / 4 If you randomly generate N points inside the sq., approximatelyN * Π / 4 of those points (M) should fall inside the circle. Π is then approximated as:N * Π / 4 = MΠ / 4 = M / NΠ = 4 * M / N Note that expanding the number of issues generated improves the approximation. Serial pseudo code for this procedure: npoints = 10000 circle_count = 0 do j = 1,npoints generate 2 random numbers between 0 and 1 xcoordinate = random1 ycoordinate = random2 if (xcoordinate, ycoordinate) within circle then circle_count = circle_count + 1 end do PI = 4.0*circle_count/npointsThe drawback is computationally intensive—maximum of the time is spent executing the loop Questions to invite: Is this downside ready to be parallelized? How would the issue be partitioned? Are communications needed? Are there any information dependencies? Are there synchronization needs? Will load balancing be a concern? Parallel Solution Another downside that's smooth to parallelize: All level calculations are impartial; no data dependencies Work will also be flippantly divided; no load stability concerns No need for communique or synchronization between duties Parallel technique: Divide the loop into equivalent portions that may be executed by means of the pool of tasks Each project independently performs its work A SPMD type is used One task acts because the master to assemble effects and compute the price of PI Pseudo code answer: pink highlights adjustments for parallelism. npoints = 10000 circle_count = 0 p = number of duties num = npoints/p to find out if I am MASTER or WORKER do j = 1,num generate 2 random numbers between Zero and 1 xcoordinate = random1 ycoordinate = random2 if (xcoordinate, ycoordinate) inside of circle then circle_count = circle_count + 1 end do if I'm MASTER obtain from WORKERS their circle_counts compute PI (use MASTER and WORKER calculations) else if I'm WORKER ship to MASTER circle_count endifExample Programs Simple Heat Equation Most problems in parallel computing require verbal exchange some of the duties. A host of commonplace issues require verbal exchange with "neighbor" duties. The 2-D heat equation describes the temperature trade over time, given initial temperature distribution and boundary prerequisites. A finite differencing scheme is hired to solve the warmth equation numerically on a square region. The parts of a 2-dimensional array constitute the temperature at points at the square. The preliminary temperature is zero on the limitations and high within the heart. The boundary temperature is held at 0. A time stepping set of rules is used. The calculation of a component relies on neighbor component values: A serial program would contain code like: do iy = 2, big apple - 1 do ix = 2, nx - 1 u2(ix, iy) = u1(ix, iy) + cx * (u1(ix+1,iy) + u1(ix-1,iy) - 2.*u1(ix,iy)) + cy * (u1(ix,iy+1) + u1(ix,iy-1) - 2.*u1(ix,iy)) finish do end doQuestions to ask: Is this downside in a position to be parallelized? How would the issue be partitioned? Are communications needed? Are there any data dependencies? Are there synchronization needs? Will load balancing be a priority? Parallel Solution This drawback is tougher, since there are information dependencies, which require communications and synchronization. The whole array is partitioned and allotted as subarrays to all duties. Each assignment owns an equivalent portion of the entire array. Because the volume of work is equal, load balancing should now not be a concern Determine data dependencies: Implement as an SPMD model: Master process sends initial information to workers, and then waits to collect results from all staff Worker processes calculate resolution within specified number of time steps, speaking as essential with neighbor processes Pseudo code answer: purple highlights adjustments for parallelism. to find out if I'm MASTER or WORKER if I'm MASTER initialize array ship each and every WORKER beginning information and subarray obtain effects from each and every WORKER else if I am WORKER obtain from MASTER beginning information and subarray # Perform time steps do t = 1, nsteps update time ship neighbors my border info receive from neighbors their border info update my portion of resolution array finish do send MASTER results endifExample Programs 1-D Wave Equation In this example, the amplitude alongside a uniform, vibrating string is calculated after a specified quantity of time has elapsed. The calculation comes to: the amplitude on the y axis i as the location index alongside the x axis node points imposed along the string replace of the amplitude at discrete time steps. The equation to be solved is the one-dimensional wave equation: A(i,t+1) = (2.0 * A(i,t)) - A(i,t-1) + (c * (A(i-1,t) - (2.0 * A(i,t)) + A(i+1,t)))

the place c is a continuing

Note that amplitude is dependent upon earlier timesteps (t, t-1) and neighboring issues (i-1, i+1). Questions to invite: Is this problem in a position to be parallelized? How would the issue be partitioned? Are communications needed? Are there any information dependencies? Are there synchronization needs? Will load balancing be a concern? 1-D Wave Equation Parallel Solution This is another instance of an issue involving knowledge dependencies. A parallel answer will contain communications and synchronization. The whole amplitude array is partitioned and distributed as subarrays to all tasks. Each task owns an equal portion of the full array. Load balancing: all issues require equivalent work, so the points should be divided similarly A block decomposition would have the work partitioned into the number of tasks as chunks, permitting each and every assignment to own most commonly contiguous information issues. Communication need handiest happen on data borders. The better the block dimension the less the communique. Implement as an SPMD fashion: Master process sends preliminary information to staff, after which waits to gather effects from all staff Worker processes calculate resolution within specified quantity of time steps, communicating as essential with neighbor processes Pseudo code resolution: purple highlights changes for parallelism. find out quantity of tasks and assignment identities #Identify left and right neighbors left_neighbor = mytaskid - 1 right_neighbor = mytaskid +1 if mytaskid = first then left_neigbor = remaining if mytaskid = remaining then right_neighbor = first find out if I'm MASTER or WORKER if I am MASTER initialize array ship each and every WORKER starting data and subarray else if I am WORKER` receive beginning data and subarray from MASTER endif #Perform time steps #In this example the master participates in calculations do t = 1, nsteps send left endpoint to left neighbor receive left endpoint from right neighbor ship proper endpoint to right neighbor receive proper endpoint from left neighbor #Update points along line do i = 1, npoints newval(i) = (2.0 * values(i)) - oldval(i) + (sqtau * (values(i-1) - (2.0 * values(i)) + values(i+1))) end do finish do #Collect effects and write to record if I'm MASTER receive effects from every WORKER write results to file else if I'm WORKER send effects to MASTER endifExample Programs This completes the educational. Evaluation Form

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References and More Information

Author: Blaise Barney, Livermore Computing (retired) Contact: [email protected] A seek on the Web for "parallel programming" or "parallel computing" will yield a wide variety of information. Recommended reading: Photos/Graphics have been created by way of the writer, created through different LLNL staff, obtained from non-copyrighted, executive or public domain (similar to http://commons.wikimedia.org/) assets, or used with the permission of authors from other presentations and internet pages. History: These fabrics have advanced from the next assets, which might be no longer maintained or available. Tutorials located within the Maui High Performance Computing Center's "SP Parallel Programming Workshop". Tutorials advanced via the Cornell University Center for Advanced Computing (CAC), now to be had as Cornell Virtual Workshops at: https://cvw.cac.cornell.edu/topics.

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